Method for forming a metallization layer

ABSTRACT

A method for forming a metallization layer. A first layer is formed outwardly from a semiconductor substrate. Contact vias are formed through the first layer to the semiconductor substrate. A second layer is formed outwardly from the first layer. Portions of the second layer are selectively removed such that the remaining portion of the second layer defines the layout of the metallization layer and the contact vias. The first and second layers are electroplated by applying a bi-polar modulated voltage having a positive duty cycle and a negative duty cycle to the layers in a solution containing metal ions. The voltage and surface potentials are selected such that the metal ions are deposited on the remaining portions of the second layer. Further, metal ions deposited on the first layer during a positive duty cycle are removed from the first layer during a negative duty cycle. Finally, exposed portions of the first layer are selectively removed.

[0001] This application is a Divisional of U.S. patent application Ser. No. 09/652,619, filed Aug. 31, 2000, which is a Continuation of U.S. patent Application Ser. No. 08/912,051, filed Aug. 18, 1997, now U.S. Pat. No. 6,144,095, which is a Continuation of U.S. patent application Ser. No. 08/656,712, filed Jun. 3, 1996, now U.S. Pat. No. 5,662,788.

TECHNICAL FIELD OF THE INVENTION

[0002] The present invention relates generally to integrated circuits and, in particular, to a method for forming a metallization layer.

BACKGROUND OF THE INVENTION

[0003] An integrated circuit comprises a large number of semiconductor devices, such as transistors, that are formed on a semiconductor substrate or, more colloquially, a “chip.” These devices are selectively interconnected by one or more patterned layers of a conductive material, typically aluminum, to form a circuit that performs a desired function. These layers are referred to as “metallization” layers. As integrated circuits become more complex, designers reduce the minimum feature size of the constituent devices of the circuit, so as to fit more devices on a chip. With this reduction in size, it becomes more difficult to achieve proper pattern definition using conventional techniques such as photolithography and dry etch techniques for forming metallization layers. Further, designers have attempted to use copper instead of aluminum as the principle metallization material in the metallization layers, due to perceived advantages in resistivity, ductility and melting point. Unfortunately, developers have not been able to create a reliable technique for patterning a copper layer.

[0004] For example, one process using electro-deposition for forming a copper metallization layer is described in U.S. Pat. No. 5,151,168. According to this process, a conductive barrier layer is deposited on a semiconductor substrate. Further, a photoresist reverse image of the maskwork normally used to etch the metallization pattern is created on the substrate. The wafer is then transferred to an electrolytic bath in which the copper is complexed with EDTA molecules. A fixed voltage is applied between a voltage source and the semiconductor substrate to deposit the copper ions on the barrier layer that is not covered by the photoresist layer including contact/via openings on the semiconductor substrate. Unfortunately, when the substrate is placed in the electrolytic bath, the photoresist material may lift-off from the substrate thus depositing copper in areas where it is not required.

[0005] For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a method for forming a metallization layer that avoids the disadvantages and problems of prior techniques.

SUMMARY OF THE INVENTION

[0006] A method for forming a metallization layer is described which uses a single electro-deposition step to reliably form both the metallization layer and to fill the contact vias. In particular, one embodiment of the present invention uses first and second layers of materials that are placed at different surface potentials to form the metallization layer. The first layer is formed outwardly from a semiconductor substrate. Contact vias are formed through the first layer to the semiconductor substrate. The second layer is formed outwardly from the first layer. Portions of the second layer are selectively removed such that the remaining portion of the second layer defines the layout of the metallization layer and the contact vias. Metal ions in a solution are electro-deposited by applying a bi-polar modulated voltage having a positive duty cycle and a negative duty cycle to the layers and the solution. The voltage and surface potentials are selected such that the metal ions are deposited on the remaining portions of the second layer. Further, metal ions deposited on the first layer during a positive duty cycle are removed from the first layer during a negative duty cycle. Finally, exposed portions of the first layer are selectively removed.

[0007] In another embodiment of the present invention, the first and second layers are placed at different surface potentials by applying a first voltage to a surface of the first layer and applying a second voltage, higher than the first voltage, to the second layer. In another embodiment of the present invention the different surface potentials are achieved in part by selecting materials for the first and second layers that have different innate surface potentials.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008]FIGS. 1A through 1D are cross-sectional views of a semiconductor substrate that illustrate process steps according to an illustrative embodiment of the present invention.

[0009]FIGS. 2 and 3 are cross-sectional views of additional illustrative embodiments of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0010] In the following detailed description of the invention, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be used and that logical, mechanical and electrical changes may be made without departing from the spirit and scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense.

[0011]FIGS. 1A through 1D are cross-sectional views of semiconductor substrate 10 that depict process steps according to an illustrative embodiment of the present invention. Advantageously, the illustrative embodiment forms a metallization layer, including filling contact vias, outwardly from semiconductor substrate 10 in a single electro-deposition step. The process exposes adjacent layers of materials that are formed outwardly from semiconductor substrate 10 with different surface potentials to a bi-polar modulated voltage source to deposit the metallization layer and to fill the contact vias. The surface potentials and the modulated voltage are selected such that the metallization layer forms only on the second layer because metal that deposits on the first layer during a first duty cycle of the bi-polar modulated voltage is removed from the first layer during a second duty cycle.

[0012] As shown in FIG. 1A, borophosphosilicate glass (BPSG) layer 12 is deposited and reflowed outwardly from semiconductor substrate 10. First layer 14 is formed outwardly from BPSG layer 12. First layer 14 may comprise, for example, poly-silicon, doped or undoped, that is deposited using a conventional chemical vapor deposition (CVD) or sputtering technique. Alternatively, other materials such as germanium may be substituted for the poly-silicon. Contact via 16 is etched through first layer 14 and BPSG layer 12 to, for example, junction 18 of semiconductor substrate 10. Second layer 20 is formed outwardly from first layer 14 so as to line contact via 16 and cover first layer 14 by, for example, depositing a layer of titanium nitride or other appropriate barrier layer material using a conventional sputter or chemical vapor deposition technique. First layer 14 and second layer 20 have a thickness on the order of 100 to 500 Å. Advantageously, the innate surface potential of first layer 14 is lower than the innate surface potential of second layer 20. This difference in surface potentials contributes to the selectivity of the electro-deposition step described below. In other embodiments, first and second layers 14 and 20 can be fabricated from other materials that provide similar differences in innate surface potential.

[0013] Portions of second layer 20 are selectively removed such that the remaining portions of second layer 20 match the desired pattern for the metallization layer, including contact vias. As shown in FIG. 1B, layer 22, comprising, for example, a conventional photoresist material, is formed outwardly from layer 20 using conventional techniques. Layer 22 is exposed through a mask. Portions of layer 22 are removed with a solvent so as to produce a patterned layer of photoresist material that matches the desired metallization layer. The exposed portions of layer 20 are removed with, for example, a dry etch leaving a patterned version of layer 20. Layer 22 is removed. Once layer 20 is patterned, semiconductor substrate 10 is placed in an electrolytic bath for electro-deposition of the metallization layer outwardly from layer 20 so as to fill contact vias 16. The bath includes metal ions in a solution. For example, the metal ions may comprise copper ions in a solution as described in U.S. Pat. No. 5,151,168 entitled “Process for Metallizing Integrated Circuits With Electrically Deposited Copper” (the “'168 Patent”), the teachings of which are incorporated by reference. Specifically, one embodiment of the electrolytic bath is described in the '168 Patent at Column 5, lines 10 through 35. Alternatively, the electrolytic bath may comprise a solution containing nickel or palladium ions.

[0014] Voltage source 26 provides a bipolar modulated voltage to anode 28 and voltage source 24 provides a DC offset voltage to anode 28. The voltage on anode 28 causes metal ions to be deposited on a layer when the potential difference between anode 28 and the surface potential of the layer exceeds the reduction potential of the metal. Conversely, the voltage on anode 28 causes metal ions to be removed from the surface of a layer when the potential difference between anode 28 and the surface potential of the layer is less than the reverse deposition potential of the metal. The voltages of sources 26 and 28 are selected such that metal deposited on layer 14 during a first duty cycle is removed during a second duty cycle. Further, metal is not removed from layer 20 during the second duty cycle. For example, in one embodiment source 26 provides a square wave with a de offset provided by source 24 such that during the positive duty cycle of source 26, metal ions deposit on layers 14 and 20 and during the negative duty cycle copper is etched from layer 14. In other embodiments, source 26 comprises other time-varying wave-forms such as a triangle wave, sinusoidal wave or other appropriate voltage wave form.

[0015] Once the deposition of metallization layer 30 is complete, exposed portions. of first layer 14 are removed leaving the structure shown in FIG. 1D. In one embodiment, metallization layer 30 covers all of the exposed surfaces of layer 20 as shown in FIG. 2. It is understood that an integrated circuit constructed according to this process would include a complete metallization layer with a plurality of contact vias even though only portions of the metallization layer and a single contact via are shown in FIGS. 1A through 1D.

Conclusion

[0016] Although an illustrative embodiment has been described herein, it will be appreciated by those of ordinary skill in the art that any arrangement which is calculated to achieve the same purpose may be substituted for the specific embodiment shown. This application is intended to cover any adaptations or variations of the illustrative embodiment. For example, the type of modulated voltage can be varied from the specified square wave used in the illustrative embodiment. Further, the difference in surface potential between layers 14 and 20 can be imposed or enhanced by applying voltages to the surfaces of layers 14 and 20. In this embodiment, layers 14 and 20 are separated by insulating layer 15 as shown in FIG. 3. The composition of the electrolytic bath can be varied so long as metal ions deposit on layer 20 when sources 24 and 26 are applied to anode 28. 

What is claimed is:
 1. A method for forming a metallization layer outwardly from a semiconductor substrate, the method comprising the steps of: forming a first layer of a material outwardly from the semiconductor substrate; forming contact vias that extend through the first layer to the semiconductor substrate; forming a layer of a second material outwardly from the first layer; selectively removing portions of the second layer such that the remaining portion of the second layer defines the layout of the metallization layer and the contact vias; placing the first and second layers at different surface potentials; electro-depositing the first and second layers in a solution of metal ions by applying a bi-polar modulated voltage having a positive duty cycle and a negative duty cycle, the voltage and surface potentials selected such that the metal is deposited on the remaining portions of the second layer and that metal deposited on the first layer during a positive duty cycle is removed from the first layer during a negative duty cycle; and selectively removing exposed portions of the first layer.
 2. The method of claim 1, wherein the step of depositing a first layer comprises depositing a layer of poly-silicon outwardly from the semiconductor substrate.
 3. The method of claim 1, wherein the step of electroplating comprises the steps of: depositing the semiconductor substrate in an electrolytic bath containing a metal having a reduction potential; and exposing the bath to a modulated voltage such that during a positive duty cycle the metal is deposited on exposed surfaces of the first layer and the second layer and that during a negative duty cycle the metal is removed from the exposed surface of the first layer.
 4. The method of claim 1, wherein the step of depositing a second layer comprises depositing a layer of titanium nitride.
 5. The method of claim 3, wherein the step of depositing the semiconductor substrate in an electrolytic bath comprises the step of depositing the semiconductor substrate in an electrolytic bath containing copper ions.
 6. The method of claim 1, wherein the step of placing the first and second layers at different surface potentials comprises the step of applying a first voltage to a surface of the first layer and applying a second voltage, different than the first voltage, to the second layer, wherein the first and second layers are separated by an insulating layer.
 7. The method of claim 1, wherein the step of placing the first and second layers at different surface potentials comprises the step of selecting a material for the first layer that has an innate surface potential that is less than the innate surface potential for the material selected for the second layer.
 8. The method of claim 1, wherein the step of electroplating the first and second surfaces comprises the step of electroplating the first and second surfaces with a voltage source that produces a substantially square wave voltage output.
 9. A method for forming a metallization layer outwardly from a semiconductor substrate, the method comprising the steps of: forming a first layer of a material outwardly from the semiconductor substrate, the first layer having a first innate surface potential; forming contact vias that extend through the first layer to the semiconductor substrate; forming a layer of a second material outwardly from the first layer so as to line the contact vias and cover the first layer, the second layer having a second innate surface potential different from said first innate surface potential; selectively removing portions of the second layer such that the remaining portion of the second layer defines the layout of the metallization layer and the contact vias; placing the semiconductor substrate with the first and second layers in an electrolytic bath comprising a solution of metal ions; applying a bi-polar modulated voltage having a positive duty cycle and a negative duty cycle to the electrolytic bath, the voltage and surface potentials selected such that the metal is deposited on the remaining portions of the second layer and that metal deposited on the first layer during a positive duty cycle is removed from the first layer during a negative duty cycle; and selectively removing exposed portions of the first layer.
 10. The method of claim 9, wherein the step of depositing a first layer comprises depositing a layer of poly-silicon outwardly from the semiconductor substrate.
 11. The method of claim 9, wherein the step of placing the semiconductor substrate with the first and second layers in an electrolytic bath comprises the step of placing the semiconductor substrate with the first and second layers in an electrolytic bath containing copper ions in solution.
 12. The method of claim 9, wherein the step of depositing a second layer comprises depositing a layer of titanium nitride.
 13. The method of claim 9, and further comprising the step of imposing an external voltage to one of the first and second layers to place the first and second layers at different surface potentials.
 14. The method of claim 9, and further comprising the step of placing the first and second layers at different surface potentials by applying a first voltage to a surface of the first layer and applying a second voltage, different from the first voltage, to the second layer, wherein the first and second layers are separated by an insulating layer.
 15. The method of claim 9, wherein the step of electroplating the first and second surfaces comprises the step of electroplating the first and second surfaces with a voltage source that produces a substantially square wave voltage output.
 16. An integrated circuit, comprising: a plurality of semiconductor devices formed on a semiconductor substrate; a metallization layer formed outwardly from the semiconductor substrate that selectively interconnects the semiconductor devices so as to be operable to perform a function; a first patterned layer of material formed outwardly from the semiconductor substrate that matches the metallization pattern; and a second patterned layer of material, formed between the metallization layer and the first patterned layer, that matches the metallization pattern and lines contact vias that extend through the first layer to the semiconductor substrate.
 17. The integrated circuit of claim 16, wherein the metallization layer comprises copper deposited on the second layer in an electrolytic bath.
 18. The integrated circuit of claim 16, wherein the first layer comprises poly-silicon.
 19. The integrated circuit of claim 16, wherein the second layer comprises titanium nitride.
 20. The integrated circuit of claim 16, wherein the metallization layer comprises copper.
 21. A semiconductor manufacturing system, comprising: an electrolytic bath containing metal ions; an anode; and a modulating voltage supply to provide a bipolar modulated voltage between a substrate of a semiconductor device and the anode in the presence of the electrolytic bath, and wherein the modulated voltage has a first duty cycle and a second duty cycle, wherein the metal ions are deposited on an exposed first layer of the semiconductor device and on a second layer of the semiconductor device during the first duty cycle, and wherein the metal ions are removed from the exposed first layer during the second duty cycle.
 22. The semiconductor manufacturing system of claim 21, wherein the first layer has a first surface voltage and the second layer has a second surface voltage, and the first surface voltage is lower than the second surface voltage.
 23. The semiconductor manufacturing system of claim 21, further comprising a voltage supply circuit to supply a first potential to the exposed first layer and a second potential to the second layer.
 24. The semiconductor manufacturing system of claim 23, wherein the voltage supply circuit includes a first voltage supply to supply a first potential to the exposed first layer, and a second voltage supply to supply a second potential to the second layer.
 25. The semiconductor manufacturing system of claim 21, wherein the electrolytic bath contains copper ions to form a copper metallization layer.
 26. The semiconductor manufacturing system of claim 21, wherein the electrolytic bath contains nickel ions to form a nickel metallization layer.
 27. The semiconductor manufacturing system of claim 21, wherein the electrolytic bath contains palladium ions to form a palladium metallization layer.
 28. A semiconductor manufacturing system for forming a metallization layer on a semiconductor device having a substrate, a first layer of material on the substrate, and a patterned second layer of material on the first layer of material, the system comprising: an anode; an electrolytic bath of metal ions for the semiconductor device; and a modulating voltage supply to provide a bipolar modulating voltage between the anode and the substrate of the semiconductor device.
 29. The semiconductor manufacturing system of claim 28, wherein the first material has a first potential and the second material has a second potential.
 30. The semiconductor manufacturing system of claim 28, comprising a voltage supply circuit to provide a first potential to the first layer of material and a second potential to the second layer of material.
 31. The semiconductor manufacturing system of claim 28, further comprising a DC offset voltage in series with the modulating voltage supply.
 32. The semiconductor manufacturing system of claim 28, wherein the modulating voltage supply includes a square wave voltage supply.
 33. The semiconductor manufacturing system of claim 28, wherein the modulating voltage supply includes a triangle wave voltage supply.
 34. The semiconductor manufacturing system of claim 28, wherein the modulating voltage supply includes a sinusoidal wave voltage supply.
 35. A semiconductor manufacturing system for forming a metallization layer on a semiconductor device having a substrate, a first layer of material on the substrate, and a patterned second layer of material on the first layer of material, the system comprising: an anode; a modulating voltage supply to provide a bipolar modulating voltage with a DC offset between the anode and the substrate of the semiconductor device; and an electrolytic bath of copper ions for the semiconductor device.
 36. The semiconductor manufacturing system of claim 35, wherein the first material has a first potential and the second material has a second potential.
 37. The semiconductor manufacturing system of claim 35, further comprising a voltage supply circuit to provide a first potential to the first layer of material and a second potential to the second layer of material.
 38. The semiconductor manufacturing system of claim 35, wherein the modulating voltage supply includes a square wave voltage supply.
 39. The semiconductor manufacturing system of claim 35, wherein the modulating voltage supply includes a triangle wave voltage supply.
 40. The semiconductor manufacturing system of claim 35, wherein the modulating voltage supply includes a sinusoidal wave voltage supply.
 41. A semiconductor manufacturing system for forming a metallization layer on a semiconductor device having a substrate, a first layer of material on the substrate, an insulator layer on the first layer of material, a patterned second layer of material on the insulator layer, the system comprising: an anode; a modulating voltage supply to provide a bipolar modulating voltage between the anode and the substrate of the semiconductor device; a circuit to provide a first potential on the first layer of material and a second potential on the second layer of material; and an electrolytic bath of metal ions for the semiconductor device.
 42. The semiconductor manufacturing system of claim 41, wherein the metal ions include copper ions.
 43. The semiconductor manufacturing system of claim 41, wherein the metal ions include nickel ions.
 44. The semiconductor manufacturing system of claim 41, wherein the metal ions include palladium ions.
 45. The semiconductor manufacturing system of claim 41, wherein: the bipolar modulating voltage has a first duty cycle and a second duty cycle; and metal ions are deposited on the first layer of material and the second layer of material during the first duty cycle, and are removed from the first layer of material during the second duty cycle.
 46. A semiconductor manufacturing system for forming a metallization layer on a semiconductor device having a substrate, a first layer of material on the substrate, and a patterned second layer of material on the first layer of material, the system comprising: an anode; a circuit to provide a first potential on the first layer of material and a second potential on the second layer of material; an electrolytic bath of metal ions for the semiconductor device; and a modulating voltage supply to provide a bipolar modulating voltage with a DC offset between the anode and the substrate of the semiconductor device, the bipolar modulating voltage having a first duty cycle and a second duty cycle, wherein metal ions are deposited on the first layer of material and the second layer of material during the first duty cycle, and are removed from the first layer of material during the second duty cycle.
 47. The semiconductor manufacturing system of claim 46, wherein the metal ions include copper ions.
 48. The semiconductor manufacturing system of claim 46, wherein the metal ions include nickel ions.
 49. The semiconductor manufacturing system of claim 46, wherein the metal ions include palladium ions.
 50. A semiconductor manufacturing system, comprising: means for forming a first layer overlying a substrate; means for forming contact vias through the first layer to the substrate; means for forming a patterned second layer overlying the first layer and lining the contact vias; and means for forming a metallization layer, including means for applying a bipolar modulated voltage between the substrate and an anode in the presence of an electrolytic bath.
 51. The semiconductor manufacturing system of claim 50, wherein the means for forming a metallization layer includes means for filling the contact vias.
 52. The semiconductor manufacturing system of claim 50, further comprising means for applying a first potential to the first layer and a second potential to the second layer.
 53. The semiconductor manufacturing system of claim 50, wherein the means for applying a bipolar modulated voltage between the substrate and an anode in the presence of an electrolytic bath includes means for providing a DC offset potential.
 54. A semiconductor manufacturing system, comprising: means for providing a semiconductor device having: a substrate; a first layer overlying the substrate; and a second layer overlying the first layer, wherein the device has an exposed first layer portion and an exposed second layer portion; and means for providing a bipolar modulated voltage between the substrate and an anode in the presence of an electrolytic bath containing metal ions, wherein the modulated voltage has a first duty cycle and a second duty cycle; wherein the metal ions are deposited on the exposed first layer portion and the exposed second layer portion during the first duty cycle; and wherein the metal ions are removed from the exposed first layer portion during the second duty cycle.
 55. The semiconductor manufacturing system of claim 54, further comprising means for applying a first potential to the first layer and a second potential to the second layer.
 56. The semiconductor manufacturing system of claim 54, wherein the means for providing a bipolar modulated voltage includes providing a DC offset potential.
 57. The semiconductor manufacturing system of claim 54, wherein the metal ions include copper ions.
 58. The semiconductor manufacturing system of claim 54, wherein the metal ions include nickel ions.
 59. The semiconductor manufacturing system of claim 54, wherein the metal ions include palladium ions. 